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Fpga Implementation of Trellis Decoders for Linear Block Codes : Volume 12, Issue 6 (10/11/2014)

By Scholl, S.

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Book Id: WPLBN0004002759
Format Type: PDF Article :
File Size: Pages 7
Reproduction Date: 2015

Title: Fpga Implementation of Trellis Decoders for Linear Block Codes : Volume 12, Issue 6 (10/11/2014)  
Author: Scholl, S.
Volume: Vol. 12, Issue 6
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection, Copernicus GmbH
Publication Date:
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications


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Leonardi, E., Scholl, S., & Wehn, N. (2014). Fpga Implementation of Trellis Decoders for Linear Block Codes : Volume 12, Issue 6 (10/11/2014). Retrieved from

Description: Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. Forward error correction based on trellises has been widely adopted for convolutional codes. Because of their efficiency, they have also gained a lot of interest from a theoretic and algorithm point of view for the decoding of block codes. In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes. A key feature is the use of a sophisticated permutation network, the Banyan network, to implement the time varying structure of the trellis. We have implemented the Viterbi and the max-log-MAP algorithm in different folded versions on a Xilinx Virtex 6 FPGA.

FPGA implementation of trellis decoders for linear block codes

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