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Fpga Implementation of Trellis Decoders for Linear Block Codes : Volume 12, Issue 6 (10/11/2014)

By Scholl, S.

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Book Id: WPLBN0004002759
Format Type: PDF Article :
File Size: Pages 7
Reproduction Date: 2015

Title: Fpga Implementation of Trellis Decoders for Linear Block Codes : Volume 12, Issue 6 (10/11/2014)  
Author: Scholl, S.
Volume: Vol. 12, Issue 6
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection, Copernicus GmbH
Historic
Publication Date:
2014
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications

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Leonardi, E., Scholl, S., & Wehn, N. (2014). Fpga Implementation of Trellis Decoders for Linear Block Codes : Volume 12, Issue 6 (10/11/2014). Retrieved from http://kindle.worldlibrary.net/


Description
Description: Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany. Forward error correction based on trellises has been widely adopted for convolutional codes. Because of their efficiency, they have also gained a lot of interest from a theoretic and algorithm point of view for the decoding of block codes. In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes. A key feature is the use of a sophisticated permutation network, the Banyan network, to implement the time varying structure of the trellis. We have implemented the Viterbi and the max-log-MAP algorithm in different folded versions on a Xilinx Virtex 6 FPGA.

Summary
FPGA implementation of trellis decoders for linear block codes

Excerpt
Bahl, L., Cocke, J., Jelinek, F., and Raviv, J.: Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate, IEEE T. Inform. Theory, IT-20, 284–287, 1974.; Benes, V. E.: Optimal Rearrangeable Multistage Connecting Networks, The Bell System Technical Journal, 4, 1641–1656, 1964.; Goke, L. R. and Lipovski, G. J.: Banyan Networks for Partitioning Multiprocessor Systems, 1st Annual Symposium on Computer Architecture, 21–28, 1973.; Hekstra, A. P.: An Alternative to Metric Rescaling in Viterbi Decoders, IEEE T. Commun., 37, 1220–1222, 1989.; Kim, S., Ryoo, S., and Lee, S.: Block Turbo Codes Using Multiple Soft Outputs, in: Proceedings of the 3rd ISTC, Vol. 1, 247–250, Brest, 2003.; Lin, S. and Costello, D.: Error Control Coding 2nd., Prentice Hall PTR, Upper Saddle River, New Jersey, USA, 2004.; Liu, C. Y. and Lin, S.: Turbo encoding and decoding of Reed-Solomon codes through binary decomposition and self-concatenation, IEEE T. Commun., 52, 1484–1493, 2004.; Pyndiah, R., Glavieux, A., Picart, A., and Jacq, S.: Near optimum decoding of product codes, in: Proc. IEEE Global Telecommunications Conf. GLOBECOM '94. Communications: The Global Bridge, 339–343, 1994.; Robertson, P., Villebrun, E., and Hoeher, P.: A Comparison of Optimal and Sub-Optimal MAP decoding Algorithms Operating in the Log-Domain, in: Proc. 1995 International Conference on Communications (ICC '95), 1009–1013, Seattle, Washington, USA, 1995.; Tanner, R. M.: A Recursive Approach to Low Complexity Codes, IEEE T. Inform. Theory, IT-27, 533–547, 1981.; Vardy, A. and Be'ery, Y.: Bit-level soft-decision decoding of Reed-Solomon codes, IEEE T. Commun., 39, 440–444, 1991.; Viterbi, A. J.: Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm, IEEE T. Inform. Theory, 13, 260–269, 1967.; Wolf, J.: Efficient maximum likelihood decoding of linear block codes using a trellis, IEEE T. Inform. Theory, 24, 76–80, 1978.

 

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